FMC407 FPGA Mezzanine Card

Clock and trigger distribution module
FMC406 FPGA Mezzanine Card

Overview

The FMC407 is a low noise clock generation and distribution module with eight clock outputs and eight trigger outputs that are fully synchronized.

There are two configurations: 34.375MHz-200MHz or 34.375MHz-4.4GHz. The FMC407 is ideal for applications that require synchronous A/D or D/A sampling across multiple cards or systems.

This module can either distribute an externally supplied or a locally generated clock. 

A synchronous trigger signal received from the FMC connector is distributed to the eight trigger outputs. Additionally, an external trigger signal can by synchronized to the output clocks and distributed on the eight trigger outputs. 

Alternatively, it is also possible to distribute the external 1PPS or locally generated 1PPS signal for data time stamping.

The FMC406 is based on Analog Devices’ ADF4351 PLL synthesizer in combination with the Cypress Semiconductor CY29948AXI LVCMOS fan-out buffer. The FMC407 is based on Analog Devices’ ADF4351 PLL synthesizer in combination with the ADCLK954 LVPECL fan-out buffer.

The LINX RXM-GPS-F4-T GPS module provides the 1PPS signal for click and trigger synchronization for both configurations.

FMC.gif

FMC.gif

Specifications

Channels
8 trigger out, 8 clock out
Cooling
Air, Conduction
Data Rate
34.375 MHz up to 4.4 GHz (clock out)
FMC Connector
LPC
Form Factor
FMC
Frequency Range
34.375 to 4400 MHz
Function
Clock Distribution and Trigger Distribution
Signaling
LVCMOS/LVDS, LVPECL (clock/trigger out)

Block Diagram

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Clock and trigger distribution module

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