- Processor clock frequency changed from 12 MHz to 16 MHz.
- Processor changed from +5v 80960JF to +3.3v 80960JS.
- Optional PC/104-Plus pass-through connector available.
- Connections provided for eight additional external discrete inputs.
This has been accomplished by routing these eight new discrete inputs to the connections also used by the eight existing discrete outputs. You must ensure that an output is not driven low if the input (sharing the same connection) is to be used (unless a wired-OR configuration is desired). This configuration also allows the inputs to be used to monitor the board discrete outputs if the added eight discrete input connections are not used.
- On-board PLD updated for new clock speed.
- The FPGA configuration file and processor firmware (contained in a file downloaded to the board) have been changed.
- For customer applications using the Condor-supplied API (Application Programming Interface), these changes are transparent (i.e., Version 3.20 (and higher) of CEI-x20-SW contains the changes).
- CEI-x20-SW Version 3.20 (and higher) supports both the CEI-420 and the CEI-420A running in the same system.
- Existing customer CEI-420 programs have to be relinked with the new CEI-x20-SW libraries, and the new CEI-420A installation software must be executed. For 32-bit Windows, uninstall the previous CEI-x20-SW before installing the new API. For LINUX and other operating systems, user programs need to be relinked and recompiled with the new libraries.