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Description
Slow PCI bus performance when a PCI master device abandons a cycle that was Retry terminated by the PCI-5565 or PMC-5565 products.
This condition can occur when a PCI master abandons an access to the 5565 that was terminated with Retry and then asserts an access to a different address instead of retrying the original access. The 5565 will respond to all subsequent accesses with Retry until either the originally retried access is completed or the 5565 Discard Timer register expires and flushes the original address information from its FIFO.
Per the PCI bus Spec. 2.2:
"A master which is target terminated with Retry must unconditionally repeat the same request until it completes."
To prevent deadlocks on the PCI bus the PCI Spec. allows the use of a Discard Timer that expires after 2^15 PCI clock cycles.
Note: When a PCI master abandons a retried access and consequently all subsequent accesses are retried until the discard timer expires, the PCI bus can be noticeably slowed or even appear to be locked up.
Resolution
To workaround this condition the Delayed Read Mode bit 24 should be cleared in the MARBR register and bits 31:28 should be set in the LBRD0 register (Direct Slave Retry Delay Clocks 8*F). This will increase the amount of time the 5565 is given to respond to an access and should prevent the 5565 from responding to any access with Retry.
Note: The attached patch file was written for a GE FANUC RFM2G driver as workaround to the above described condition and can be used as an example of what needs to be modified in a user's kernel level routine.
References
3.3.3.2.2 of the PCI2.2 Spec.
Programming Section of either PCI-5565 or PMC-5565 manuals.