Share
To access flash memory on PMC557 in linear mode you must find the value in the PCI header BAR0 (header offset 0x10) where the vendor ID (header offset 0x0) is 0x140B and the device ID (header offset 0x02) is 0xF557. You must add 0x1000000 to the value in BAR0. For instance if BAR0 reports 0x4000000 the first accessible address would be 0x4000000 + 0x1000000 = 0x5000000. This is because the embedded processor of the PMC557, the i960 CPU, uses two flash chips in parallel for 32-bit operations and these two chips are logically located in the lower PCI-MEM for the PMC557. This in effect renders the first 16MB (two chips) inaccessible linearly from the host that the PMC557 in installed on.
Also, the first 4 bits of BAR0 are configuration bits when reported in the PCI header. If BAR0 is set to 0x4000008 the first accessible address would also be 0x4000000 + 0x1000000 = 0x5000000.
Lastly, make sure the PCI command register (header offset 0x04) is set to 0x2 to enable PCI-MEM transactions.